Phase locked loops are well known in the art. With reference to FIG. 1, a typical prior art phase locked loop includes a phase detector (A), a filter (B), a voltage controlled oscillator (C), and a divide-by-N unit (D). An input signal (F.sub.i) having a first frequency can be input to the phase detector (A). The output of the phase detector (A), after being filtered by the filter (B), provides a drive signal for the voltage controlled oscillator (C).
Through a feedback loop, the output of the voltage controlled oscillator (C) is divided by N and used by the phase detector (A) as a reference signal for comparison with the incoming signal (F.sub.i). By virtue of this comparison, the output of the phase detector (A) comprises a signal that relates to the degree to which the input signal and the reference signal are in phase with one another.
When locked, the output signal from the voltage controlled oscillator (C) will have a frequency (F.sub.o) equal to N times the frequency of the input signal (F.sub.i). As one example, if N equals 1, the frequency of the output signal will equal the frequency of the input signal.
Depending upon the application, there are problems that arise when using such phase locked loops. For instance, the locking speed of a phase locked loop can vary with the frequency of the incoming signal. In general, the lower the frequency of the incoming signal, the longer the lock in time due to corner frequency needs.
Certain applications display particular sensitivity to such a time delay. For example, consider the pilot tone component of a transmitted AM stereo signal. Upon sensing this pilot tone signal, a radio receiver can ignite a "Stereo" indicator lamp and activate the associated stereo matrix network. In these respects, the use of a pilot tone in the AM stereo setting essentially parallels the use of a pilot tone in FM stereo broadcasting. Unlike FM pilot tones, however, the AM stereo pilot tone has a low frequency (25 Hz) and is broadcast with only 5 percent modulation. This relatively slowly cycling, low amplitude signal makes detection by a prior art phase locked loop time consuming. Through use of ordinary techniques, locking onto such a signal will often take many seconds. This constitutes an unacceptable delay in such a product.
There therefore exists a need for a phase locked loop device that can quickly lock on a low frequency signal.